A next-generation electronic product is asked to have multiple functions and high-speed performance other than compactness. The integrated-circuit manufacturers have moved to smaller design rules to make chips with much more electronic devices. On the other hand, the techniques for packaging the chips or semiconductor substrates have also been developed for the same purpose.
Conventionally, a flip-chip chip size package (FCCSP) substrate 10 used to construct the so-called “molded interconnection substrate (MIS)” can be illustrated in FIG. 1. A photo-sensitive primer material can be used to form the dielectric material layer 17 on the molding compound layer 16, and the metal pillars 18 are used to connect the upper-layer conductive wires 14 and the lower-layer conductive wires 12. Wherein, bottom surfaces of the molding compound layer 16 and the lower-layer conductive wires 12 may be arranged in the same plane, or the molding compound layer 16 may have a bottom surface protruding from that of the lower-layer conductive wires 12 as shown in FIG. 1. Often, roughness and non-uniformity may happen on the bottom surfaces of the lower-layer conductive wires 12, and this fact would induce not-good soldering points during the soldering process and thus diminish the fabrication yield. Therefore, it is in need to develop a new means for fabricating package substrates.